www.arcadenation.com home of GALT, the Gameboy Advance Learning Tool - Created in 2002 by Ian Edmundson.
The information contained in this page is provided as a complement to the register viewer on the Gameboy Advance emulator.
5. SYSTEM/ INTERRUPT REGISTERS
Register name:
VID_DISPLAY_CONTROL
Memory offset: 0x4000000
There are 6 video modes on the gameboy advance. Mode 0 provides tile based
output on the BG0 through BG3 layers. Mode 1 provides tile based output on the
BG0 and BG1 layers. The BG2 layer is used for rotation/scaling. Mode 2 provides
rotation and scaling on layers BG2 and BG3. Modes 3 and 5 provide a 15bit pixel
output. Mode 4 provides an 8bit pixel output at 240x160. Mode 3 provides a
resolution of 240x160, but full VRAM is used thus not allowing for
double-buffering.
Mode 4 allows for double buffering as there is space in VRAM for two video pages. The current displayed video page is specified in the FRAMEBUFFER bit of this register. Mode 5 has a resolution of 160x128, also allowing video page swapping. Tiles are restricted to 8x8 pixels in all tile based video modes. This allows for displaying 30x20 tiles on screen, although the tile map can be up to 64x64 in size.The tile map can be shifted in the x or y through the VID_BGx_HSCROLL and VID_BGx_VSCROLL registers.
Tiles can be 16 colour or 256 colour. All tiles work from the same palette, so it is possible to have 16 different palettes of 16 when using 16 colour tiles. All 256 colour tiles work from the same palette. Palette index 0 is always the transparent colour. The GBA uses 128 entries in SPRITE memory for sprite attributes. Each of these entries are 4x16bit.
Tile mode screen resolution can be anything from 256x256 to 1024x1024?. All videomodes provide for a background image that can be seen through the transparent pixels of the BG0 through BG3 layers. The pixel values in the 8bit video mode specify the offset in palette memory. Two different palettes can be stored in palette memory at one time, with each entry containing a 16 bit colour value.The second of these palettes is used for sprite colours. 16bit colour is made up from 5bits red, 5bits green, and 5bits blue. The FORCEDBLANK bit does as it says, but the screen goes white when it is triggered.
Register name: VID_DISPLAY_STATUS
Memory offset: 0x4000004
1,2 and 3 are all updated by the controller. 4,5 and 6 are set to enable IRQ.
The Y trigger value is the current y co-ordinate being written by the display.
Register name: VID_CURRENT_SCANLINE
Memory offset: 0x4000006
This register contains the current scanline.
Register name:
VID_BG0_CONTROL
Memory offset: 0x4000008
TILE_BASEADDR contains the start address of the tile data (MEM_VIDEOMEMORYOFFSET+addr*0x4000).
SCREEN_BASE contains the start address of the tile map (MEM_VIDEOMEMORYOFFSET+addr*0x800).
SCREENSIZE can be 00: 256x256 (32*32 tiles), 01: 512*256 (64*32 tiles), 10:
256x512 (32*64 tiles), 11: 512*512 (64*64 tiles). Bits 4,5 are set to 0.
Register name:
VID_BG1_CONTROL
Memory offset: 0x400000A
TILE_BASEADDR contains the start address of the tile data (MEM_VIDEOMEMORYOFFSET+addr*0x4000).
SCREEN_BASE contains the start address of the tile map (MEM_VIDEOMEMORYOFFSET+addr*0x800).
SCREENSIZE can be 00: 256x256 (32*32 tiles), 01: 512*256 (64*32 tiles), 10:
256x512 (32*64 tiles), 11: 512*512 (64*64 tiles). Bits 4,5 are set to 0.
Register name: VID_BG2_CONTROL
Memory offset: 0x400000C
TILE_BASEADDR contains the start address of the tile data (MEM_VIDEOMEMORYOFFSET+addr*0x4000).
SCREEN_BASE contains the start address of the tile map (MEM_VIDEOMEMORYOFFSET+addr*0x800).
SCREENSIZE can be 00: 256x256 (32*32 tiles), 01: 512*256 (64*32 tiles), 10:
256x512 (32*64 tiles), 11: 512*512 (64*64 tiles). Bits 4,5 are set to 0.
Register name:
VID_BG3_CONTROL
Memory offset: 0x400000E
TILE_BASEADDR contains the start address of the tile data (MEM_VIDEOMEMORYOFFSET+addr*0x4000).
SCREEN_BASE contains the start address of the tile map (MEM_VIDEOMEMORYOFFSET+addr*0x800).
SCREENSIZE can be 00: 256x256 (32*32 tiles), 01: 512*256 (64*32 tiles), 10:
256x512 (32*64 tiles), 11: 512*512 (64*64 tiles). Bits 4,5 are set to 0.
Register name:
VID_BG0_HSCROLL
Memory offset: 0x4000010
Background 0 (BG0) horizontal scroll offset.
Register name:
VID_BG0_VSCROLL
Memory offset: 0x4000012
Background 0 (BG0) vertical scroll offset.
Register name:
VID_BG1_HSCROLL
Memory offset: 0x4000014
Background 1 (BG1) horizontal scroll offset.
Register name:
VID_BG1_VSCROLL
Memory offset: 0x4000016
Background 1 (BG1) vertical scroll offset.
Register name:
VID_BG2_HSCROLL
Memory offset: 0x4000018
Background 2 (BG2) horizontal scroll offset.
Register name:
VID_BG2_VSCROLL
Memory offset: 0x400001A
Background 2 (BG2) vertical scroll offset.
Register name:
VID_BG3_HSCROLL
Memory offset: 0x400001C
Background 3 (BG3) horizontal scroll offset.
Register name:
VID_BG3_VSCROLL
Memory offset: 0x400001E
Background 3 (BG3) vertical scroll offset.
Register name:
VID_BG2_HSTEPX
Memory offset: 0x4000020
Background 2 (BG2) horizontal texture step in X value.
Register name:
VID_BG2_VSTEPX
Memory offset: 0x4000022
Background 2 (BG2) vertical texture step in X value.
Register name:
VID_BG2_HSTEPY
Memory offset: 0x4000024
Background 2 (BG2) horizontal texture step in Y value.
Register name:
VID_BG2_VSTEPY
Memory offset: 0x4000026
Background 2 (BG2) vertical texture step in Y value.
Register name:
VID_BG2_XSTARTL
Memory offset: 0x4000028
Low 16 bits of X co-ordinate reference start point (Rotation and scaling
results).
Register name:
VID_BG2_XSTARTH
Memory offset: 0x400002A
High 12 bits of X co-ordinate reference start point (Rotation and scaling
results).
Register name:
VID_BG2_YSTARTL
Memory offset: 0x400002C
Low 16 bits of Y co-ordinate reference start point (Rotation and scaling
results).
Register name:
VID_BG2_YSTARTH
Memory offset: 0x400002E
High 12 bits of Y co-ordinate reference start point (Rotation and scaling
results).
Register name:
VID_BG3_HSTEPX
Memory offset: 0x4000030
Background 3 (BG3) horizontal texture step in X value.
Register name:
VID_BG3_VSTEPX
Memory offset: 0x4000032
Background 3 (BG3) vertical texture step in X value.
Register name: VID_BG3_HSTEPY
Memory offset: 0x4000034
Background 3 (BG3) horizontal texture step in Y value.
Register name:
VID_BG3_VSTEPY
Memory offset: 0x4000036
Background 3 (BG3) vertical texture step in Y value.
Register name:
VID_BG3_XSTARTL
Memory offset: 0x4000038
Low 16 bits of X co-ordinate reference start point (Rotation and scaling
results).
Register name:
VID_BG3_XSTARTH
Memory offset: 0x400003A
High 12 bits of X co-ordinate reference start point (Rotation and scaling
results).
Register name:
VID_BG3_YSTARTL
Memory offset: 0x400003C
Low 16 bits of Y co-ordinate reference start point (Rotation and scaling
results).
Register name:
VID_BG3_YSTARTH
Memory offset: 0x400003E
High 12 bits of Y co-ordinate reference start point (Rotation and scaling
results).
Register name:
VID_WIN0X
Memory offset: 0x4000040
Window 0 X co-ordinates. 8 bits LEFT, 8 bits RIGHT.
Register name:
VID_WIN1X
Memory offset: 0x4000042
Window 1 X co-ordinates. 8 bits LEFT, 8 bits RIGHT.
Register name:
VID_WIN0Y
Memory offset: 0x4000044
Window 0 Y co-ordinates. 8 bits BOTTOM, 8 bits TOP.
Register name:
VID_WIN1Y
Memory offset: 0x4000046
Window 1 Y co-ordinates. 8 bits BOTTOM, 8 bits TOP.
Register name:
VID_WININ
Memory offset: 0x4000048
Inside window settings. e.g. Background 0 in Window 0 (BG0WIN0).
Register name:
VID_WINOUT
Memory offset: 0x400004A
Outside window and sprite window. e.g. Background 0 outside Window 0 (BG0WIN).
Register name:
VID_MOSAIC_CONTROL
Memory offset: 0x400004C
Background X size (BGX). Background Y size (BGY). Sprite X size (SPRITEX).
Sprite Y size (SPRITEY).
Register name:
VID_BLEND_CONTROL
Memory offset: 0x4000050
Blend control register. Bits 6,13 are reserved.
Register name:
VID_BLEND_COEFFAB
Memory offset: 0x4000052
Blend coefficients A and B.
Register name:
VID_BLEND_COEFFY
Memory offset: 0x4000054
Blend coefficient Y.
Register name: DMA_CHAN0_SRCL
Memory offset: 0x40000B0
Low 16 bits: DMA channel 0 source address.
Register name:
DMA_CHAN0_SRCH
Memory offset: 0x40000B2
High 11 bits: DMA channel 0 source address.
Register name:
DMA_CHAN0_DESTL
Memory offset: 0x40000B4
Low 16 bits: DMA channel 0 destination address.
Register name:
DMA_CHAN0_DESTH
Memory offset: 0x40000B6
High 11 bits: DMA channel 0 destination address.
Register name:
DMA_CHAN0_SIZE
Memory offset: 0x40000B8
Channel 0 transfer size.
Register name:
DMA_CHAN0_CONTROL
Memory offset: 0x40000BA
Channel 0 control register. Destination mode (DESTMODE) can have value 00:
Increment and writeback, 01: Decrement and writeback, 10: Fixed, and 11:
Increment. Source mode (SOURCEMODE) can have value 00: Increment and writeback,
01: Decrement and writeback, or 10: Fixed. When a start mode is selected and the
REPEAT bit is set, DMA will continue to occur each interval until the enable bit
in the control register is cleared. The amount of data transferred is specified
by both the count register for a DMA channel, and the WIDTH bit. The WIDTH bit
indicates either a halfword (0) or word (1) transfer. Start mode (STARTMODE) can
have values 00: Immediately, 01: V-Blank, or 10: H-Blank.
Register name:
DMA_CHAN1_SRCL
Memory offset: 0x40000BC
Low 16 bits: DMA channel 1 source address.
Register name:
DMA_CHAN1_SRCH
Memory offset: 0x40000CE
High 12 bits: DMA channel 1 source address.
Register name:
DMA_CHAN1_DESTL
Memory offset: 0x40000C0
Low 16 bits: DMA channel 1 destination address.
Register name:
DMA_CHAN1_DESTH
Memory offset: 0x40000C2
High 11 bits: DMA channel 1 destination address.
Register name:
DMA_CHAN1_SIZE
Memory offset: 0x40000C4
DMA channel 1 size
Register name:
DMA_CHAN1_CONTROL
Memory offset: 0x40000C6
Channel 1 control register. Destination mode (DESTMODE) can have value 00:
Increment and writeback, 01: Decrement and writeback, 10: Fixed, and 11:
Increment. Source mode (SOURCEMODE) can have value 00: Increment and writeback,
01: Decrement and writeback, or 10: Fixed. When a start mode is selected and the
REPEAT bit is set, DMA will continue to occur each interval until the enable bit
in the control register is cleared. The amount of data transferred is specified
by both the count register for a DMA channel, and the WIDTH bit. The WIDTH bit
indicates either a halfword (0) or word (1) transfer. Start mode (STARTMODE) can
have values 00: Immediately, 01: V-Blank, or 10: H-Blank.
Register name:
DMA_CHAN2_SRCL
Memory offset: 0x40000C8
Low 16 bits: DMA channel 2 source address.
Register name:
DMA_CHAN2_SRCH
Memory offset: 0x40000CA
High 12 bits: DMA channel 1 source address.
Register name:
DMA_CHAN2_DESTL
Memory offset: 0x40000CC
Low 16 bits: DMA channel 2 destination address.
Register name:
DMA_CHAN2_DESTH
Memory offset: 0x40000CE
High 11 bits: DMA channel 2 destination address.
Register name:
DMA_CHAN2_SIZE
Memory offset: 0x40000D0
DMA channel 2 size
Register name:
DMA_CHAN2_CONTROL
Memory offset: 0x40000D2
Channel 2 control register. Destination mode (DESTMODE) can have value 00:
Increment and writeback, 01: Decrement and writeback, 10: Fixed, and 11:
Increment. Source mode (SOURCEMODE) can have value 00: Increment and writeback,
01: Decrement and writeback, or 10: Fixed. When a start mode is selected and the
REPEAT bit is set, DMA will continue to occur each interval until the enable bit
in the control register is cleared. The amount of data transferred is specified
by both the count register for a DMA channel, and the WIDTH bit. The WIDTH bit
indicates either a halfword (0) or word (1) transfer. Start mode (STARTMODE) can
have values 00: Immediately, 01: V-Blank, or 10: H-Blank.
Register name:
DMA_CHAN3_SRCL
Memory offset: 0x40000D4
Low 16 bits: DMA channel 3 source address.
Register name:
DMA_CHAN3_SRCH
Memory offset: 0x40000D6
High 12 bits: DMA channel 1 source address.
Register name:
DMA_CHAN3_DESTL
Memory offset: 0x40000D8
Low 16 bits: DMA channel 3 destination address.
Register name:
DMA_CHAN3_DESTH
Memory offset: 0x40000DA
High 12 bits: DMA channel 3 destination address.
Register name:
DMA_CHAN3_SIZE
Memory offset: 0x40000DC
DMA channel 3 size
Register name:
DMA_CHAN3_CONTROL
Memory offset: 0x40000DE
Channel 3 control register. Destination mode (DESTMODE) can have value 00:
Increment and writeback, 01: Decrement and writeback, 10: Fixed, and 11:
Increment. Source mode (SOURCEMODE) can have value 00: Increment and writeback,
01: Decrement and writeback, or 10: Fixed. When a start mode is selected and the
REPEAT bit is set, DMA will be processed until the enable bit in the control
register is cleared. The amount of data transferred is specified by both the
count register for a DMA channel, and the WIDTH bit. The WIDTH bit indicates
either a halfword (0) or word (1) transfer. Start mode (STARTMODE) can have
values 00: Immediately, 01: V-Blank, or 10: H-Blank. Bit 11 is a reserved bit.
Register name:
TMR_VALUE0
Memory offset: 0x4000100
16 bit timer value.
Register name:
TMR_CONTROL0
Memory offset: 0x4000102
The counter increments the TMR_VALUE0 register according to the set frequency.
FREQUENCY can have value 00: increment by 1 per clock, 01: increment by 0.015625
per clock (1 over 64), 10: increment by 0.00390625 per clock (1 over 256), or
increment by 0.0009765625 per clock (1 over 1024). The CASCADE bit have no
effect on this timer. ENABLED bit must be set for timer to proceed. If the IRQ
bit is set, the timer will generate and interrupt request on overflow.
Register name:
TMR_VALUE1
Memory offset: 0x4000104
16 bit timer value.
Register name:
TMR_CONTROL1
Memory offset: 0x4000106
The counter increments the TMR_VALUE1 register according to the set frequency.
FREQUENCY can have value 00: increment by 1 per clock, 01: increment by 0.015625
per clock (1 over 64), 10: increment by 0.00390625 per clock (1 over 256), or
increment by 0.0009765625 per clock (1 over 1024). The CASCADE bit allows for
TIMER0 to be run on overflow. ENABLED bit must be set for timer to proceed. If
the IRQ bit is set, the timer will generate and interrupt request on overflow.
Register name:
TMR_VALUE2
Memory offset: 0x4000108
16 bit timer value.
Register name:
TMR_CONTROL2
Memory offset: 0x400010A
The counter increments the TMR_VALUE2 register according to the set frequency.
FREQUENCY can have value 00: increment by 1 per clock, 01: increment by 0.015625
per clock (1 over 64), 10: increment by 0.00390625 per clock (1 over 256), or
increment by 0.0009765625 per clock (1 over 1024). The CASCADE bit allows for
TIMER1 to be run on overflow. ENABLED bit must be set for timer to proceed. If
the IRQ bit is set, the timer will generate and interrupt request on overflow.
Register name:
TMR_VALUE3
Memory offset: 0x400010C
16 bit timer value.
Register name:
TMR_CONTROL3
Memory offset: 0x400010E
The counter increments the TMR_VALUE3 register according to the set frequency.
FREQUENCY can have value 00: increment by 1 per clock, 01: increment by 0.015625
per clock (1 over 64), 10: increment by 0.00390625 per clock (1 over 256), or
increment by 0.0009765625 per clock (1 over 1024). The CASCADE bit allows for
TIMER2 to be run on overflow. ENABLED bit must be set for timer to proceed. If
the IRQ bit is set, the timer will generate and interrupt request on overflow.
Register name:
PAD_STATUS
Memory offset: 0x4000130
Each bit is set when a button on the pad is released.
Register name:
PAD_INT_STATUS
Memory offset: 0x4000132
If FLAG is 0, any key can trigger an interrupt. If set to 1, all keys pressed
triggers an interrupt.
Register name:
PAD_BUS_FLAG
Memory offset: 0x4000134
Register name:
PAD_BUS_CONTROL
Memory offset: 0x4000140
Register name:
PAD_BUS_RECEIVEL
Memory offset: 0x4000150
Register name:
PAD_BUS_RECEIVEH
Memory offset: 0x4000152
Register name:
PAD_BUS_SENDL
Memory offset: 0x4000154
Register name:
PAD_BUS_SENDH
Memory offset: 0x4000156
Register name:
PAD_RECEIVE_STATUS
Memory offset: 0x4000158
Register name:
INT_MASTER_ENABLE
Memory offset: 0x4000200
Enable interrupts for corresponding system component.
Register name:
INT_FLAG
Memory offset: 0x4000202
If an interrupt is generated by a system component, the corresponding bit is set
to 1.
Register name:
SYS_WAIT_STATE_CONTROL
Memory offset: 0x4000204
Wait state control. Values of PHI are 00 : no output, 01: 4.19 MHz 10: 8.38 MHz
, or 11: 16.76 MHz. Prefetch allows forward reading of cart rom (consumes 10%
more power on GBA console). Values are set by the system upon booting cartridge.
Register name:
SYS_PAUSE
Memory offset: 0x4000300
If MODE is set, system goes into a waiting state.